1. Field of the Invention
The present invention relates to a charge pump circuit and, more particularly, to a charge pump circuit capable of generating a soft-start pumping voltage for so appropriately driving a power switch as to suppress maximum inrush current upon activation.
2. Description of the Related Art
Charge pump circuits, or capacitive voltage multipliers, are circuits that generate a voltage larger than a supply voltage from which the charge pump circuits operate. With such voltage boosting ability, the charge pump circuits can be applied to provide from a single supply voltage source desired pumping voltages for electronics systems consisting of various components that operate with different voltages, such as portable computers, thereby avoiding additional employment of independent high voltage sources.
On the other hand, a variety of peripheral devices coupled to the portable computers through universal serial bus (USB) or other type connecting ports also need power from the supply voltage source. In this case, the charge pump circuits may be applied to drive power switches, which are typically implemented by NMOS transistors and provided to control switching operations between the supply voltage source and the peripheral devices. Through supplying a gate electrode of the NMOS power switch transistor with a voltage much higher than that at its drain electrode, the charge pump circuits can so fully turn on the NMOS power switch transistor as to provide a minimum ON resistance during normal operations of the peripheral devices.
FIG. 1(a) is a circuit block diagram showing a conventional charge pump circuit 11 applied to drive a power switch 10. Referring to FIG. 1(a), the power switch 10 implemented by an NMOS transistor has a drain electrode D as an input terminal and a source electrode S as an output terminal. The drain electrode D of the power switch 10 is connected to a supply voltage source Vin while the source electrode S provides an output voltage Vout for external loads (not shown), such as the peripheral devices with USB connecting plugs. In addition, an output capacitor Co is connected between the source electrode S of the power switch 10 and a ground potential. The charge pump circuit 11 converts the supply voltage source Vin into a higher pumping voltage Vpp for controlling a gate electrode G of the power switch 10. When the voltage at the gate electrode G of the power switch 10 is considerably higher than the supply voltage source Vin at the drain electrode D, the power switch 10 is fully turned on to provide a minimum ON resistance such that the output voltage Vout at the source electrode S of the power switch 10 is almost equal to the supply voltage source Vin at the drain electrode D. As a result, the supply voltage source Vin is effectively provided to the external loads. When the power switch 10 is turned on, an ON current Ion is flowed from the supply voltage source Vin, passing the power switch 10 through the drain electrode D to the source electrode S, for supplying the external loads and the output capacitor Co.
The pumping operation of the charge pump circuit 11 is under the control of at least one overlapping or non-overlapping clock signals 13 with a constant amplitude output from a clock generator 12. Conventionally, each of the constant amplitude clock signals 13 is a pulse train in synchronization with respect to each other, whose frequency is determined by an oscillation signal 15 with a predetermined frequency output from an oscillator 14. For example, the charge pump circuit 11 may be a well-known Dickson type charge pump, as shown in FIG. 1(b). Referring to FIG. 1(b), the charge pump circuit 11 may include a plurality of serially-connected charge pump stages, one of which is labeled 110. Each charge pump stage includes a diode 111 and a pump capacitor 112, and has an input node 113 and an output node 114. In this Dickson type charge pump, the constant amplitude clock signals 13 output from the clock generator 12 are a complementary pair of clock signals CLK1 and CLK2 for driving the various pump stage capacitors. Odd-numbered pump stages are driven by the clock signal CLK1 while even-numbered pump stages are driven by the clock signal CLK2. The input node 115 of the first serially-connected charge pump stage is usually connected to the supply voltage source Vin. A final isolation diode 116 may be considered as part of the last serially-connected charge pump stage, from which the pumping voltage Vpp of the charge pump circuit 11 is asserted.
The clock signals CLK1 and CLK2 may be overlapping or non-overlapping clock signals with the constant amplitude Vclk, for boosting the voltage conveyed to its input node by an amount equal to the clock amplitude Vclk minus a forward diode drop Vd, i.e. Vclk−Vd. If the effect of the final isolation diode 116 is included, the maximum theoretical pumping voltage Vpp is equal to N·Vclk−(N+1)·Vd, where N is the number of charge pump stages.
FIGS. 2(a) to 2(c) are operational timing charts showing the conventional charge pump circuit 11 of FIG. 1(a) applied to drive the power switch 10. More specifically, FIG. 2(a) is a timing chart showing the pumping voltage Vpp generated by the charge pump circuit 11. FIG. 2(b) is a timing chart showing the output voltage Vout of the power switch 10. FIG. 2(c) is a timing chart showing the ON current Ion flowing through the power switch 10. Referring to FIG. 2(a), the pumping voltage Vpp is zero before a time TA because the charge pump circuit 11 stays at a disable state then. The charge pump circuit 11 is activated on the time TA, starting the voltage boosting operation. During a transient period from the time TA until the time TB, the pumping voltage Vpp of the charge pump circuit 11 rapidly rises from zero to a stable maximum, such as N·V−(N+1)·Vd, as described above. By the time TB the charge pump circuit 11 reaches a stable operational state at which the pumping voltage Vpp remains stable.
Referring to FIGS. 2(b) and 2(c), the power switch 10 is turned off before the activation time TA since the pumping voltage Vpp of the charge pump circuit 11 is smaller than a threshold voltage of the power switch 10, so the output voltage Vout is zero and the ON current Ion is also zero. After the pumping voltage Vpp of the charge pump circuit 11 rises above the threshold voltage, the power switch 10 is turned on to start charging the output capacitor Co, resuiting in an increase of the output voltage Vout of the power switch 10. Since the pumping voltage Vpp of the charge pump circuit 11 drives the power switch 10 to provide the minimum ON resistance, the output voltage Vout of the power switch 10 almost reaches the supply voltage source Vin by a time TC.
When applied to drive the power switch 10, the conventional charge pump circuit 11 inevitably brings about a problem on the activation of the power switch 10. Due to the rapid increase of the pumping voltage Vpp of the charge pump circuit 11, it takes a relatively short time after the activation for the power switch 10 to provide the minimum ON resistance. However, since the output voltage Vout is zero upon the activation time because the output capacitor Co has not yet been charged, the supply voltage source Vin produces through the power switch 10 an extremely large ON current Ion, i.e. the inrush current. If the maximum inrush current Ipeak receives no cure or appropriate suppression, the supply voltage source Vin possibly drops with a great degree during the activation or the power switch 10 may even be burned by the maximum inrush current Ipeak.